National Workshop on Integrated Circuit (IC) Design 2025

FROM 08 Dec 2025 TO 12 Dec 2025

Venue : Hybrid (Venue: Manipal University Jaipur (MUJ), Jaipur) @

This workshop aims to enhance the skills and technical competence of students and faculty members in the field of VLSI design. It offers a comprehensive overview of the integrated circuit (IC) design flow and provides hands-on experience in schematic design, circuit simulation, and layout development. Participants will also gain familiarity with industry-standard electronic design automation (EDA) tools and the practical challenges encountered in modern VLSI design. Through this program, attendees will gain valuable insights into current industrial practices and emerging trends, contributing to the development of a skilled workforce aligned with the goals of the India Semiconductor Mission (ISM).

The workshop is organized by the Department of Electronics and Communication Engineering, Manipal University Jaipur, in collaboration with the Department of Electrical Engineering, Dayalbagh Educational Institute (DEI), Agra.

This initiative will also support compliance with the requirements of the Chips to Startup (C2S) programme of MeitY for EDA tool support.

Important Dates

Registration Deadline: 08.12.2025

Registration and Payment Details:

Fees: ₹100 Includes: Kit, Refreshments (in-person).
Payment Here: https://rzp.io/rzp/tr9IhkCL
Register Here (After payment): https://forms.gle/QjyShEGETVTKU6fb7

Contact us:

syed.askari@jaipur.manipal.edu

+91 97989 08669